VHDL Verilog Integer Arrays Ports -

i working on project fpga implementation of breakout game. in game, have break bricks using ball , paddle. bricks may break on multiple contacts ball. this, using integer array represent number of hits required break particular brick. eg (2,0,1,2) represents brickk needs 2 hits broken followed broken brick followed brick needs single hit broken et al.

also, have done coding in vhdl in order output results onto vga screen, using verilog.

in vhdl, have declared type integer array in package follows:

package mytypes_pkg     type int_array array (0 39) of integer; end mytypes_pkg; 

then in ball motion controlling file, have imported work.mytypes_pkg.all , have:

brickout:out int_array; 

which contains current state of bricks in game. array has passed verilog file vga display generation has take place. there, tried

input [39:0]    bricki; 

but gives me error

"different types port 'brickout' on entity , component 'mainc'"

how can rectify error , want do? there way of telling verilog bricki of type int_array? , need import work.mytypes_pkg.all in verilog too?

in systemverilog can use typedef define own types, e.g.

typedef int [n-1:0] mytype; 

and way build want. define types in package , import it:

import pkg_keccak::mytype; ... mytype int_table;