vhdl - 8 bit ALU for microprocessor -


i have project supposed develop risc microprocessor . involves creating alu in behavioral model . there seems problems/errors/warnings while simulating design . of operations work except following :

comparing 2 inputs : when numbers equal , 0 flag not getting set . ( unequal numbers working ) .

warning: there 'u'|'x'|'w'|'z'|'-' in arithmetic operand, result 'x'(es).

( appears every 1 ps , presumably due wait statement in process )

i wish work std_logic_vector, though read messy .

also, there problem when try use comparing commands ( update flags dont store difference in output register ) . how if commands executed in vhdl ?? executed @ same time ?? or line line ??

code below :

   library ieee;   use ieee.std_logic_1164.all;   use ieee.std_logic_arith.all;   use ieee.std_logic_unsigned.all;   entity alu   port(       input1 , input2: in std_logic_vector(7 downto 0 ) ;        carryin : in std_logic ;         zero,carryout : out std_logic ;         output : out std_logic_vector(7 downto 0 ) ;         control : in std_logic_vector(7 downto 0 )           ) ;  end alu ;   architecture operation of alu signal tmp : std_logic_vector( 8 downto 0 ) ;  begin process begin   if( control = "00110000" or control(7 downto 3 )  = "00001" ) tmp <= carryin & ( input1 , input2 ) ;   elsif( control(7 downto 3 ) = "00010" ) tmp <= carryin & ( input1 or input2 ) ;   elsif( control(7 downto 3 ) = "00011" ) tmp <= carryin & ( input1 xor input2 ) ;   elsif( control(7 downto 3 ) = "00100" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)+1 ) , 9 ) ;    elsif( control(7 downto 3 ) = "00101" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)-1 ) , 9 ) ;    elsif( control = "10001100" ) tmp <= '0' & (not input1) ;    elsif( control(7 downto 3 ) = "11000" or control(7 downto 2 ) = "110010" or control = "110-11--" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)+conv_integer(input2) ) , 9 ) ;    elsif( control(7 downto 3 ) = "11100" or control(7 downto 2 ) = "111010" or control = "111-11--" or control(7 downto 3 ) = "00000" or control = "00111000" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)-conv_integer(input2) ) , 9 ) ;    elsif( control(7 downto 3 ) = "11010" or control(7 downto 2 ) = "110110" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)+conv_integer(input2)+conv_integer(carryin) ) , 9 ) ;   elsif( control(7 downto 3 ) = "11110" or control(7 downto 2 ) = "111110" ) tmp <= conv_std_logic_vector(  ( conv_integer(input1)-conv_integer(input2)-conv_integer(carryin) ) , 9 ) ;   end if ;   if ( tmp( 7 downto 0 ) = "00000000" ) 0 <= '1' ;   else 0 <= '0' ;         end if ;        if( control(7 downto 3 ) = "00000" or control = "00111000" )       tmp( 7 downto 0 ) <= input1 ;        end if ;       output <= tmp( 7 downto 0 ) ;      carryout <= tmp(8) ;       wait 1 ps; end process ;  end operation ;

testbench code

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;   entity test_tb end test_tb;  architecture behavior of test_tb    component alu   port(       input1 , input2: in std_logic_vector(7 downto 0 ) ;        carryin : in std_logic ;         zero,carryout : out std_logic ;         output : out std_logic_vector(7 downto 0 ) ;         control : in std_logic_vector(7 downto 0 )           ) ;  end component ;       signal i1,i2,ctrl,opt : std_logic_vector(7 downto 0 ) := "00000000" ;    signal cin,cout,zero : std_logic := '0';   begin      uut: alu port map ( i1,i2,cin,zero,cout,opt,ctrl ) ;     stim_proc: process    begin                  i1 <= "10000000" ;          i2 <= "10000000" ;          ctrl <= "11011010" ;          cin <= '0' ;          wait 5 ps;         ctrl <= "00111000" ;          wait 5 ps ;          wait;   end process;  end;

unfortunately, piece of code doesn't expect:

control = "111-11--"

it compares control see if has 4th, 6th , 7th bits set -, rather using them "don't care" matches! mind-boggling, that's way it's been specified work years :(

what want is

 std_match(control, "111-11--")

which don't-care comparison expect.


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