verilog - Use SystemVerilog parameters to decide which module to instantiate -

is there way select module want instantiate using parameter values passed parent module? example below

module parent ();   parameter word = 1;    child_`word child (); // not work  endmodule 

if word == 1, instantiate child_1 module, word == 2, child_2 module , on. surely, has had need before?

if want conditionally instantiate module, need use generate block.

generate   if (word == 1) begin     child_1 child();   end   if (word == 2) begin     child_2 child();   end endgenerate 

below full working example. note accounts presence of child_1 , child_2. cannot use parameter part of module type name instantiating. if have n child modules , don't want explicitly enumerate them in generate block, need create helper macro.

btw, valid verilog code; doesn't use systemverilog features.

module child_1();   initial begin     $display("child_1 %m");   end endmodule  module child_2();   initial begin     $display("child_2 %m");   end endmodule  module parent();   parameter word = 1;    // conditionally instantiate child_1 or child_2 depending    // depending on value of word parameter.   generate     if (word == 1) begin       child_1 child();     end     if (word == 2) begin       child_2 child();     end   endgenerate  endmodule  module top();   parent #(.word(1)) p1();   parent #(.word(2)) p2(); endmodule 

output incisive:

child_1 top.p1.genblk1.child child_2 top.p2.genblk2.child