c++ - Makefile: no rule to make target -

i looking solution on site , tried google time now, somehow can't work.

my source should in src directory , object files in obj directory. try create simple makefie either error there no rule, or can't make work use directories.

cc = /usr/bin/gcc cxxflags =  -o2 -g -wall -fmessage-length=0  src:=       nohupshd.cpp \             task.cpp  obj:=       nohupshd.o \             task.o  objdir:=        obj srcdir:=        src  dep:=       src/task.h libs:=  target:=    nohupshd  all:    $(target)  $(target):  $(obj)     $(cc) -o $(target) $(obj) $(libs)  clean:     rm -f $(obj) $(target) 

variant 1:

$(objdir)/%.o: $(srcdir)/%.cpp     $(cc) -s $(srcdir)/$< -o $(objdir)/$@     $(cc) -c $(srcdir)/$< -o $(objdir)/$@ 

variant 1a:

%.o: %.cpp     $(cc) -s $(srcdir)/$< -o $(objdir)/$@     $(cc) -c $(srcdir)/$< -o $(objdir)/$@ 

when use pattern error there no rule nohupshd.o build.

variant 2:

$(obj) : $(objdir)/%.o: $(srcdir)/%.cpp     $(cc) -s $(srcdir)/$< -o $(objdir)/$@     $(cc) -c $(srcdir)/$< -o $(objdir)/$@ 

when use variant, can see tries build, errors saying "file".o doesn't fit target pattern.

another issue "$<" doesn't give me source name. according several sites should, can see in output there nothing, how can fix this?

update:

in meantime newest version looks this:

$(objdir)/$(obj) : $(objdir)/%.o : $(srcdir)/%.cpp     $(cc) -s $< -o $(objdir)/`basename $@ .o`.asm     $(cc) -c $< -o $@ 

this manages compile first objectfile (nohupshd.o) when make tries second file fails again saying: target 'task.o' doesn't match pattern.

you have couple if incorrect things above.

first write my error was, assuming pattern %.o matches pattern ending .o doesn't; that's not true. pattern does match string ending in .o. however, pattern character % matched on target side replaced on prerequisite side identical string. if have target obj/task.o , matches pattern %.o stem (what manual calls it) obj/task, , when prerequisite %.c means make prerequisite obj/task.c. since there isn't one, , make doesn't know how build one, rule discarded not applying. when writing pattern rules must write them only identical parts of names match pattern character (%). non-identical parts, including directories, must specified explicitly.

second, rule $(obj) : $(src) not right. line says each object file depends on all source files, whenever single source file changes all object files recompiled. that's not want (if want don't need make: can write simple shell script). don't know mean since rules empty invokes pattern rule; don't need invoke pattern rule. target depends on $(obj), , each object file depends on source file (due pattern). don't need line @ all.

third, don't know why trying construct .asm files rather compiling directly source object, if want them cleaner , more "make-like" create separate pattern rule build them: create pattern rule $(objdir)/%.o : $(objdir)/%.asm , rule $(objdir)/%.asm : $(srcdir)/%.c. if want asm files products of build should declare them prerequisite of all or similar, otherwise they'll deleted intermediate files.

fourth, using things basename unnecessary. there lots of automatic make variables can used instead. example, $* expands stem, write $(objdir)/$*.asm. of course if make separate pattern rule asm files can use $@ or $< directly. there various make functions can used; see manual.

fifth, define variable containing header file, dep, never use it. because it's not used, if change file nothing rebuilt. if know source files include every header can use $(obj) : $(dep) define that; mean (as in second point above) change header causes objects recompile. better off auto-generating prerequisites; since you're using gcc quite simple.

sixth, you're using c++ files (xxx.cpp) you're using c compiler. not work (the link line fail: although compiler can see you're compiling c++ file , right thing, if call gcc, when link bunch of objects has no idea if c objects or c++ objects (or fortran or whatever) must use c++ front-end link or won't pull in right c++ libraries). should using make variable cxx build c++ code, not cc, , setting g++ not gcc.

seventh, don't need .suffixes: .c .o use pattern rules. needed suffix rules, don't have here. can keep plain .suffixes: though disable built-in pattern matching slight performance improvement.

finally, you'll note don't need $(src) variable because make can infer pattern rules. however, if wanted have makefile less onerous change, construct contents of obj variable src variable, src = nohupshd.cpp task.cpp obj = $(patsubst %.c,$(objdir)/%.o,$(src)).

so, all-in, how recommend write makefile (i don't include auto-generated dependencies here though):

.suffixes:  cxx :=      g++ cxxflags := -o2 -g -wall -fmessage-length=0  objdir :=   obj srcdir :=   src  target :=   nohupshd src :=      nohupshd.cpp task.cpp dep :=      src/task.h libs :=  # ----  obj :=      $(patsubst %.cpp,$(objdir)/%.o,$(src)) asm :=      $(patsubst %.cpp,$(objdir)/%.asm,$(src))  .phony: clean  all: $(target) $(asm)  $(target): $(obj)         $(cxx) -o $@ $^ $(libs)  clean:         rm -f $(objdir)/* $(target)  $(objdir)/%.o : $(srcdir)/%.asm         $(cxx) $(cxxflags) -c -x assembler-with-cpp $< -o $@  $(objdir)/%.asm : $(srcdir)/%.cpp         $(cxx) $(cppflags) -s $< -o $@