xilinx - VHDL Synthesis - FF/Latch Constant Value -

i trying synthesize vhdl module have written.

the code below:

library ieee; use ieee.std_logic_1164.all;  -- uncomment following library declaration if using -- arithmetic functions signed or unsigned values use ieee.numeric_std.all;  entity clockcounter     port(         clk         : in std_logic;         input       : in std_logic;         enable      : in std_logic;         output      : out std_logic := '0';         bitready    : out std_logic := '0';         counterror  : out std_logic := '0'     ); end clockcounter;  architecture behavioral of clockcounter  signal totalbitwidth     : integer := 4; signal majorityvalue     : integer := 3;  begin  totalbitwidth <= 4; majorityvalue <= 3;  -- process recognizing single input value  clock cycle -- wide input signal majority_proc: process(clk, input, enable)      variable clkcount : integer := 0;     variable sum      : integer := 0;      begin      if rising_edge(clk) , enable = '1'         -- reset bitready after 1 clock cycle         bitready <= '0';          -- check input value , add sum variable         if input = '1'             sum := sum + 1;         else             sum := sum + 0;         end if;          -- increment clock counter variable         clkcount := clkcount + 1;          -- check if clock count has reached specified number of cycles         if clkcount >= totalbitwidth             -- determine if sum variable has met threshold             -- value of 1, set output accordingly             if sum >= majorityvalue                 output <= '1';             else                 output <= '0';             end if;              -- checks if value clock cycles same ,             -- sets error flag if not             if sum = totalbitwidth or sum = 0                 counterror <= '0';             else                 counterror <= '1';             end if;              -- reset clock counter , sum value             clkcount := 0;             sum := 0;             -- set bit counter high alert other midules new bit             -- has been received             bitready <= '1';         end if;         elsif enable = '0'         clkcount := 0;         sum := 0;     end if;      end process;      end behavioral; 

the problem getting when trying synthesize:

warning:xst:1293 - ff/latch has constant value of 0 in block . ff/latch trimmed during optimization process. warning:xst:1896 - due other ff/latch trimming, ff/latch has constant value of 0 in block . ff/latch trimmed during optimization process. warning:xst:1896 - due other ff/latch trimming, ff/latch has constant value of 0 in block . ff/latch trimmed during optimization process.

the trimming goes way down .

what don't clkcount variable integer increments 6 @ most, , reset 0.

are these warnings can ignore?

this module apart of larger system working on, , when synthesize larger system lot of

found 1-bit latch signal

so trying eliminate many warning possible in lower level modules before fixing upper level module.

any great. thanks

ps - using xilinx spartan 6 sp605 evaluation kit board, , project navigator.

from looks of it, is doing intended optimizations. clkcount declared integer or 32 bits, have reset 0 once hits majority value or 3, equates "11" or 2 bits. therefore clkcount(31 downto 2) optimized out since it's 0.

i assume sum should optimized down, synthesis tool may not notice coupling optimized well.

i'm not big fan of hard-coded values , expand generics make more customizable if instantiate multiple clock counters.

library ieee; use ieee.std_logic_1164.all;  -- uncomment following library declaration if using -- arithmetic functions     signed or unsigned values use ieee.numeric_std.all; entity clockcounter   generic (     totalbitwidth : integer := 4;     majorityvalue : integer := 3);   port(     clk        : in  std_logic;     input      : in  std_logic;     enable     : in  std_logic;     output     : out std_logic := '0';     bitready   : out std_logic := '0';     counterror : out std_logic := '0'); end clockcounter;  architecture behavioral of clockcounter   begin  -- process recognizing single input value clock cycle -- wide input     signal    majority_proc : process(clk, input, enable)      variable clkcount : integer := 0;     variable sum      : integer := 0;    begin      if rising_edge(clk) , enable = '1'                                         -- reset bitready after 1 clock cycle       bitready <= '0';                                         -- check input value , add sum     variable       if input = '1'         sum := sum + 1;       else         sum := sum + 0;       end if;                                          -- increment clock counter variable       clkcount := clkcount + 1;                                          -- check if clock count has reached     specified number of cycles        if clkcount >= totalbitwidth                                         -- determine if sum variable has met threshold                                         -- value of 1, set output accordingly         if sum >= majorityvalue           output <= '1';         else           output <= '0';         end if;                                          -- checks if value clock cycles same ,                                         -- sets error flag if not         if sum = totalbitwidth or sum = 0           counterror <= '0';         else           counterror <= '1';         end if;                                          -- reset clock counter , sum value         clkcount := 0;         sum      := 0;                                         -- set bit counter high alert other midules new bit                                         -- has been received         bitready <= '1';       end if;     elsif enable = '0'       clkcount := 0;       sum      := 0;     end if;    end process;  end behavioral;