timedelay - Verilog Time delay calculation -

i writing simple code project, has calculate time. have 2 switches, & b. want start time when pressed , stop when b pressed. maybe can store time variable , output var 7 segment! ( need timing part, 7 seg ok)

i have no background in verilog, , can't lot of online, can please give me hint.

note: apparently, has in verilog, , has in *.v format

thanks,

i start recommending find guide verilog , have @ that, need find simulator test code.

now assuming measuring clock cycles between button presses need start counter on , stop on b. possibly using , b control fsm, in turn controls counter.

things of , b external , asynchronous need put through meta stability flip-flops. depending on mechanical switches may need add more denouncing them.

i going add code since not know verilog should broken down smaller steps giving full solution, feel rob of learning experience.

if want see code verilog stop watch simplefpga.blogspot.co.uk seems reasonable.

as learning verilog hardware description langage, first think problem , trying achieve. counter, state machine. move on implementing basic version of need adding features require then.

may free running counter overflows. free running counter stops @ max value. counter starts when button pressed, counter starts when button pressed , stops when button pressed.

then can ask questions better suited q&a format of site. eg trying implement counter part of verilog stop watch, not sure how imply functionality x.

try not daunted language , if possible enjoy process of learning new skills.